Video Presentations and Tutorials
Technical Tutorial: "SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling"
Presented by Martin Vlach, Mentor Graphics; Scott Little, Intel
This tutorial provides an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard. The tutorial covers requirements and areas of concern for the new standard, data types, the new nodetype, connectivity, hierarchy, adapters, power-aware, filtering, and other concepts.
Technical Tutorial: "SVA Advanced Topics: SVAUnit and Assertions for Formal"
Presented by Ionut Ciocirîan, AMIQ; Andra Radu, AMIQ; Rodrigo Calderón-Rico, Intel; Israel Tapia, Intel
- SystemVerilog Assertions Verification with SVAUnit
- Formal Specification, SystemVerilog Assertions & Coverage
Technical Tutorial: "Cut Your Design Time in Half with Higher Abstraction"
Presented by Bob Condon, Intel; Frederic Doucet, Qualcomm; Peter Frey, Mentor Graphics; Mike Meredith, Cadence; Dirk Seynhaeve, Intel
- How High-level Synthesis Works: An Intro for Hardware Designers
- The Proposed Accellera SystemC Synthesizable Subset
- High-Level Synthesis and Verification
- HLS in the Wild — Intel's Experience
- HLS for the FPGA/Programmable Market
- SystemC Synthesis Standard: Which Topics for Next Round?
Technical Tutorial: "UVM Tips and Tricks Plus Preparing for IEEE UVM"
Presented by: Doug Perry, Doulos; Srivatsa Vasudevan, Synopsys. Slides by Srinivasan Venkataramanan, VerifWorks
- UVM Compile Time Tips and Tricks
- UVM Runtime Tips and Tricks
- Accellera Standards Update - UVM and IEEE-1800.2
Accellera Standards Technical Update
Presented by: Uwe Simm, Cadence Design Systems; Sharon Rosenberg, Cadence Design Systems; Erwin de Kock, NXP Semiconductors; Philipp A. Hartmann, Intel
Experts in the Accellera standardization give a technical update on the recent standardization activities in the various working groups: Universal Verification Methodology, Portable Stimulus, IP-XACT, and SystemC.
System-Level Modeling for Today and Tomorrow with SystemC
Presented by: Philipp A Hartmann, Intel; Martin Barnasconi, NXP; Stephan Schulz, Fraunhofer
- SystemC Standards Update
- What is Needed Beyond SystemC and TLM-2.0 for Bigger Systems?
Technical Tutorial: "SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set"
Presented by Stuart Sutherland, Sutherland HDL; Junette Tan, PMC; Mike Schaffstein, Qualcomm
- Ways Design Engineers Can Benefit from the Use of SystemVerilog Assertions
- Experience from Four Years of SVD Adoption
- No Excuses for Not Using SystemVerilog in Your Next Design
- Panel Discussion
Technical Tutorial: "Automating Design and Verification of Embedded Systems Using Metamodeling and Code Generation Techniques"
Presented by Wolfgang Ecker, Infineon; Michael Velten, Infineon; Rainer Findenig, Intel; Daniel Müller-Gritscheneder, Technical University of Munich; Wolfgang Mueller, University of Paderborn
- What Is Metamodeling and Code Generation All About
- Well Known Metamodels in EDA and Design: UML/SysML
- Well Known Metamodels in EDA and Design: IP-XACT
- Tutorial: VHDL Code Generation from IP-XACT Using the Eclipse Modeling Framework (EMF)
Technical Tutorial: "Next Generation Design and Verification Today"
Presented by Mike Bartley, TVS; Kyle Newman, Texas Instruments; Erich Marschner, Vice-Chair, IEEE P1801 WG
- Requirements-driven Verification Methodology (for Standards Compliance)
- Using UCIS to Combine Verification Data from Multiple Tools
- UVM REG: Path Towards Coverage Automation in AMS Simulations
- New Developments in UPF 3.0
Technical Tutorial: "SystemC Standardization Update Including UVM for SystemC"
Presented by Andy Goodrich, Cadence
- Accellera Systems Initiative SystemC Standards Update
- Introduction to the Universal Verification Methodology in SystemC
Technical Tutorial: "Using UPF for Low Power Design and Verification"
Presented by Erich Marschner, Mentor Graphics; John Biggs, ARM; Sushma Honnavara-Prasad, Broadcom; David Cheng, Cadence; Shreedhar Ramachandra, Synopsys
- Low Power Design and Verification Challenges
- Introduction to UPF
- UPF Basic Concepts and Terminology
- UPF Semantics and Usage
- Hard IP Modeling with Liberty and Verilog
- Power Model and Power Management Cell Commands
- Low Power Design Methodology for IP Providers
- SoC-Level Design and Verification
Technical Tutorial: "Case Studies in SystemC"
Presented by John Aynsley, Doulos; Henrik Svensson, Ericsson; Christian Sauer, Cadence; Martin Barnasconi, NXP Semiconductors; Donald Cramb, Synopsys; John Stickley, Mentor Graphics; Gordon Allen, Mentor Graphics
- Hints and Tips for Exploiting the Latest Features of SystemC
- TLM Use Cases at Ericsson AB
- Efficient Abstractions for AMS System-level Design
- UVM for SystemC Users
Technical Tutorial: "OCP: The Journey Continues"
Presented by Drew Wingard, Sonics; Steve McMaster, Synopsys; Herve Alexanian, Sonics; Prashant Karandikar, Texas Instruments
- Introduction to OCP
- Verification Support for OCP
- SystemC TLM 2.0 Support for OCP
- IP-XACT Support for OCP
- OCP Futures
Technical Tutorial: "Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0"
Presented by Martin Barnasconi, NXP Semiconductors; Karsten Einwich, Fraunhofer IIS; François Pêcheux, Université Pierre et Marie Curie; Torsten Mähne, Université Pierre et Marie Curie
- Tutorial Introduction
- SystemC AMS Introduction
- Lab: Sine Source Connected to a Sink
- Models of Computation
- Lab: Filtering and A/D Conversion
- SystemC AMS 2.0 and Applications
- Lab: Vibration Sensor
- Workshop Summary
Technical Tutorial: "UVM — What's Now and What's Next"
Presented by Adam Sherer, Accellera; John Aynsley, Doulos; Shawn Honess, Synopsys; Tom Fitzpatrick, Mentor Graphics; Uwe Simm, Cadence
- UVM Working Group Update
- UVM Overview and Library Concepts
- Stimulus Generation
- UVM Register Layer
- UVM 1.2 Introduction
Technical Tutorial: "Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™"
Presented by Erich Marschner, Mentor Graphics; Qi Wang, Cadence; John Biggs, ARM; Sushma Honnavarra-Prasad, Broadcom; Jeffrey Lee, Synopsys
- Low Power Design and Verification
- Unified Power Format (UPF)
- Power Intent Specification Methodology
- Using UPF for IP Design
- Using UPF for System Design
- What's New in UPF 2.1
Technical Tutorial: "User Experiences at the Forefront of Mixed-Signal Design and Verification"
Presented by Helene Thibieroz, Synopsys; Henry Chang, Designer's Guide Consulting; Jonathan David, Qualcomm Atheros; Christophe Curis, STMicroelectronics; Ozan Erdogan, Maxim Integrated; Martin Barnasconi, NXP Semiconductors; Thilo Voertler, Fraunhofer Institute; Thang Nguyen, Infineon
- Common Mistakes Made in Analog Verification
- The Mixed-Signal Verification Challenge
- Mixed-Signal Validations for a BIST on ADC
- SystemVerilog Modeling for Mixed-Signal SoC Verification
- AMS System-Level Design and Verification for Automotive Applications
- The VERDI Project -- Mixed-Signal Verification and Validation for SystemC/AMS
- FPGA and AMS Test Chip Approach for Complex SoC Product Design and Verification
Technical Tutorial: "Increasing Productivity with SystemC in Complex System Design and Verification"
Presented by Trevor Wieman, CCI WG Chair, Intel; David Black, Doulos; Stuart Swan, Cadence; Shabtay Matalon, Mentor Graphics; Jon McDonald, Mentor Graphics; Nithya Ruff, Synopsys; Charu Khosla, Synopsys
- Configuration, Control & Inspection Working Group Update
- A SystemC Technology Demonstrator using the Xilinx Zynq™-7000
- A Unified Design Flow for SystemC Virtual Platforms and High-Level Synthesis
- From Virtual Prototyping to RTL Verification
- Virtual Prototyping: You don't need a PHD to model in System C and TLM
Technical Tutorial: "Lessons from the Trenches: Migrating Legacy Verification Environments to UVM"
Presented by John Aynsley, Doulos; Hassan Shehab, Intel; Richard Tseng, Qualcomm; Asad Khan, Texas Instruments; Mark Litterick, Verilab; Charles Zhang, Paradigm Works; Wesley Queen, IBM; Ravi Ram, Altera
- Anecdotes from Hundreds of UVM Adopters
- Migrating from OVM to UVM — A Case Study
- A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
- UVM to the Rescue — Path to Robust Verification
- OVM-to-UVM Migration — or There and Back Again, a Consultant's Tale
- IBM Recommendations for OVM-to-UVM Migration
- FPGA Chip Verification Using UVM
Technical Tutorial: "An Introduction to IEEE 1666-2011, the New SystemC Standard"
Presented by John Aynsley, Doulos; David Black, Doulos; and Tor Jeremiassen, Texas Instruments
- SystemC Refresher
- Process Control
- Stepping and Pausing the Scheduler
- SystemC and O/S Threads
- Virtualization of SystemC Model I/O
- Draft SystemC Configuration Standard
Technical Tutorial: "Verification and Automation Improvement Using IP-XACT"
Presented by John Swanson, Synopsys; Kamlesh Pathak, STMicroelectronics; David Murray, Duolog Technologies; and Sylvain Duvillard, Magillem Design Services
- Part 1: Improving Verification Efficiency using IP-XACT
- Part 2: User Presentation: Verification and Automation Improvement Using IP-XACT
- Part 3: IP-XACT and UVM
- Part 4: IP-XACT Extensions
Technical Tutorial: "An Introduction to the Unified Coverage Interoperability Standard"
Presented by Dr. Richard Ho, D. E. Shaw Research; Dr. Ambar Sarkar, Paradigm Works, Inc.
Presented by co-chairs of the UCIS Technical Committee, this video tutorial provides an overview of UCIS and its API and how users plan to enhance their verification flows using it.
Technical Tutorial: "UVM: Ready, Set, Deploy!"
Presented by Tom Fitzpatrick, Mentor Graphics; John Aynsley, Doulos; Kathleen Meade, Cadence Design Systems; Adiel Khan, Synopsys; Vanessa Cooper, Verilab; Stephen D'Onofrio, Paradigm Works; Peter J. D'Antonio, The MITRE Corp.; John Fowler, AMD; Justin Refice, AMD; and Mark Strickland, Cisco Systems
- Part 1: Base Classes in UVM
- Part 2: Communication and Sequences
- Part 3: Customizing Your UVM Environment
- Part 4: Register Modeling in UVM
- User Experience 1: Getting Started with UVM
- User Experience 2: Stacking Verification Components in UVM
- User Experience 3: OVM to UVM Transition
- User Experience 4: VC Building Blocks with UVM
Software-driven Verification using TLM-2.0 Virtual Platforms Video Tutorial
Presented by David Black, XtremeEDA Corporation; John Aynsley, Doulos; Bill Bunton, LSI Corporation; Volkan Esen, Infineon Technologies; and Trevor Wieman, Intel Corporation
- How We Got Here
- Software-driven Verification using TLM-2.0 Virtual Platforms
- LSI Axxia™ VDP Verification Using SystemC TLM-2.0
- Software-Driven Test Environment for TLM-IP Verification
- TLM-2.0 Hybrid Virtual Platforms
NASCUG 16 Presentations
- SystemC IP Generation from Graphics and Verification with a UVM SystemVerilog Testbench
- Verification Closure of SystemC Designs with Functional Coverage
- Standard Methodology for Configuration, Control & Inspection of Models
- Software Verification, Analysis and Profiling on SystemC TLM-2.0 Virtual Platforms
- TLM-2.0: Miracle Cure or Snake Oil?
- OSCI and IEEE P1666 Update
SystemC Day 2011
Keynote: "Navigating the SoC Era"
Jim Hogan, Vista Ventures LLC
- The New IEEE 1666 SystemC Standard
- Low-cost SystemC Acceleration on Multi-core GNU/Linux Platforms
- TLM Methodology to Enable Architecture Exploration via Co-simulation of SystemC Models with Legacy C/C++ Models
- A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 Interface
- OSCI Update
NASCUG 13 Video Presentations
- How to Create Adaptors Between Modeling Abstraction Levels
- Virtual Development Platforms -- What and How Much to Model?
- Modeling Communication Systems Using the SystemC AMS Building Block Library
- New Features for Process Control in SystemC
- Generating Workload Models from TLM-2.0 Based Virtual Platforms for Efficient Architecture Performance Analysis
OSCI TLM-2.0 Standard and Synthesizable Subset Video Tutorial
Presented by John Aynsley, Doulos; Michael McNamara, Cadence Design Systems; and Michael Meredith, Forte Design Systems
- The TLM-2.0 Standard
- Current Trends in ESL/HLS
- Why SystemC for Synthesis
- SystemC Synthesizable Subset Draft V1.3
- Lessons Learned Using SystemC Synthesis
- How SystemC HLS Fits in the Design Flow
SystemC Day 2010 Video Presentations
Keynote: "ESL: Where We Are and Where We're Going"
Gary Smith, Gary Smith EDA, California, USA
- The Metaport: A Technique for Managing Code Complexity
- OCP socket modeling with TLM-2.0
- ADL Synthesis using ArchC
- Look Ma, No Clocks! Improving Model Performance
- TLM-driven Design and Verification Methodology
Using TLM Extensions for Bus Locking and Snooping
Presented by John Aynsley, Doulos
NASCUG 11 Video Presentations
- A Tool for Assertion-Based Verification of TLM Platforms
- SystemC-AMS for the Design of Complex Analog/Mixed-signal SoCs
- Modeling a Virtual MPU
- High-speed Packet Router Development in SystemC
TLM-2.0 in Action Tutorial
An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability
- Overview of TLM-2.0 Features
- TLM Mechanics
- TLM-2.0 Nuances
- Performance Modeling Using TLM-2.0
- Applying TLM-2.0 to Legacy Platforms