DVCon 2015: Not to be Missed
By Gabe Moretti
February 23, 2015
In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera. That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years. Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.
The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages. This year's conference is the 27th and offers an expanded technical program. In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year. Although this year there will be one less tutorial than the previous year, the breath of topics is larger.
The merger of OVI and VI produced significant changes, both for DVCon and for Accellera. In 2001 DVCon boosted a more efficient organization, both for its technical program and for exhibits. The source of papers offered for acceptance increased in scope as professionals outside of the Verilog and VHDL user communities became interested in presenting papers at the conference.
As Accellera grew and widened the scope of technical subject it handled, so DVCon increased the technical segments it covered. First SystemC and shortly thereafter SystemVerilog provided interesting papers and Tutorials. The verification aspect of the conference was enlivened with focus on UVM (Universal Verification Methodology), TLM (Transaction Level Modeling), testbench construction, and various approaches to testing, including formal techniques.
As the percentage of analog circuits increased in SoC, mixed languages and mixed signal design and verification also became a topic, both in papers and in Tutorials. In fact one can quickly make a list of the most relevant issues current among electronics engineers by quickly reading the current conference program.
Yatin Trivedi, DVCon General Chair succinctly described the aim of DVCon, “DVCon continues to focus on serving the Design and Verification community. DVCon is a conference sponsored by Accellera, in order to promote the adoption of its standards and standards-based methodologies. From the days of exclusive focus on Verilog and VHDL, we have come a long way in including SystemVerilog, SystemC, UPF and UVM. As semiconductor IP became significant to our community of designers and verification engineers, the program has expanded its range of topics. However, our focus remains on design and verification."
I have been asked why designers that are not interested in testing should attend DVCon. The answer, of course, is in the name of the conference. The "D" stands for design and, as I have wrote many times already, the "V" for verification is highly impacted by how the SoC is designed. So designers and test engineers both have many reasons to attend the conference. Design and Verification functions go hand-in-hand in determining the success and both development and manufacturing costs of an SoC.
DVCon has succeeded to offer in two days technical programs of high quality and current interest over the years. The Technical Program Committee (TPC) every year receives many more high quality proposals than it can possibly accept. This year is not different. Ambar Sarkar, DVCon Program Chair, told me that: "Typically, we receive about 110-140 submissions. About 70 or so are ranked highly. This year was even better-we had almost 80 highly ranked abstracts. Of course, having only 42 slots for oral presentations meant that we had to find a way to bring the remaining 36 papers to the audience, and we have accomplished this through our increasingly-popular poster session. In the poster session, the audience can interact with the authors one-on-one. Do note that the papers accepted in the poster session undergo the same scrutiny by the TPC as in the oral sessions, and the audience gets to select the best Oral as well as the best Poster presentations."
Keynote Presentation and Other Talks
In our current semiconductor design community, the word "change" is, to say the least, an understatement. From a dizzying array of emerging "smart" niche end-products to major market trend shifts to ecosystem reconfigurations at every level, the world around us is morphing at an unprecedented pace. The challenge for IC designers to keep pace has never been greater. The good news is that we're up for it! In his presentation, Aart de Geus, Synopsys Chairman and co-CEO, will address the business and technology trends that are stretching designers' concerns beyond the traditional sand boxes of design and verification.
Also on Tuesday during the lunch sponsored by Synopsys there will be a panel discussion of users sharing their experience on the tools and methods offered by Synopsys to address design and verification challenges.
During the Wednesday lunch, sponsored by Mentor Graphics, Harry Foster and Stephen Bailey will discuss the state of verification past, present and future while examining the results from a recent industry world-wide verification study. The talk will examine how advanced techniques are taking hold in mainstream design and provide insights on the recent convergence of verification solutions to meet today's growing challenges.
The Thursday lunch is sponsored by Cadence. The company has organized a panel of verification experts to discuss their overall SoC verification and debug challenges as well as some of the solutions/debug methodologies that they have adopted to improve their overall productivity, including SoC level verification. The panelists will be: John Goodenough from ARM, David Lacey from Hewlett-Packard, and Normando Montecillo of Broadcom.
The aim of the tutorials presented on Monday and Thursday of the conference is to teach subjects that are relevant to the work done presently and, in some cases, offer a view to coming technology or methodology. Tom Fitzpatrick, DVCon Sponsored Tutorial Chair described the work of his committee this way: "DVCon continues its commitment to providing leading-edge technical content in its tutorials. This expectation was set years ago when attendees used to pay to attend the tutorials, and while the tutorials are now free of charge, we have continued our practice of keeping "marketing fluff" to a minimum. Of course, given that the Thursday tutorials are now sponsored, the presenters are allowed a small amount of leeway, but all tutorial presentations are reviewed by the Tutorials Chairs to ensure that the focus remains on teaching attendees useful information that they'll be able to apply to their own projects, either now or in the future."
Attendance to the tutorials is free for full conference registrants, while there is a small fee for those that are only visiting the exhibits.
"MathWorks is exhibiting at DVCon this year because it's the ideal venue to talk to engineers about reusing their MATLAB and Simulink models for functional verification. We view DVCon as a great investment because of its focus on the unique engineering challenges presented by verification."
Corey Mathis, Marketing Manager, MathWorks, described in this way the reason for his company to exhibit at the conference. DVCon has offered exhibits since its inception in 1988. And with very few exceptions the number of exhibitors has constantly increased every year. In the last few years the conference has had such success with exhibits that one can say without any doubt that DVCon is the place to be seen if your company offers design and verification tools and services.
Mary Owen described how her company views DVCon this way: "Xpeerant Inc. is excited to be a first time exhibitor at DVCon this year. We chose DVCon because it is the only conference that specifically focuses on our client base. We hope to establish relationships with clients that are in need of our resources and look forward to mingling with fellow design verification enthusiasts and letting them know that we can provide top notch services to help them win the race to their market window."
This year attendees wanting more face-to-face interaction will find at least 36 exhibitors, including 10 exhibiting for the first time and 6 companies headquartered outside of the US. Of the 6 international companies, 2 are exhibiting for the first time. Because of demand, exhibits will be in both the main exhibit hall, as well as the expanded foyer section.
Sunil Kakkar, GM & Chief Technologist, TVS USA put it all into focus as follows: "DVCon is the go-to conference if you want to discover not only what the best and brightest minds of the design and verification world are doing today to tackle the myriad of challenges we are all facing in areas like mixed signal or low power design or in IP reuse, but to also get a unique peek into their thought process regarding what steps the industry may take in the future to solve challenges that may not even have surfaced today."
The extraordinary success of DVCon has convinced Accellera to hold international DVCon conferences. Last year the inaugural DVCon India and DVCon Europe were held with such success that they will be repeated again this year. If you attended DVCon last year, it was the only conference organized by Accellera. This year, when you arrive at the conference, you will notice a new logo that states DVCon United States. DVCon is not only establishing itself as a leading US conference but building an international presence that will continue to provide leadership to design and verification engineers worldwide.