SystemC Evolution Day 2018
Workshop on the evolution of SystemC standards
Tuesday, October 23, 2018
Holiday Inn Munich City, Germany
The third SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC eco-system. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion.
SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together the experts from the SystemC user community and the Accellera Working Groups to advance the SystemC standards. This is the third event after a successful second edition in October 2017.
Date / Time: October 23, 2018 (day before DVCon Europe 2018) | 10:00 - 18:00
Location: Holiday Inn Munich City Centre, Hochstrasse 3, 81669 Munich, Germany | Hotel details
Organization Team: Philipp A. Hartmann, Intel; Oliver Bell, Intel; Martin Barnasconi, NXP; Joachim Geishauser, NXP; Matthias Bauer, Infineon; Volkan Esen, Infineon; Andrew Stevens, Infineon
Preliminary, Subject to change. Please check back for updates.
|09:30 – 10:00||Welcome coffee|
|Brief SystemC Working Groups standardization update|
|10:45 – 11:15|
|11:15 – 11:45||Coffee break|
|12:45 – 14:00||Lunch break*|
|15:30 – 16:00||Coffee break|
|#5: TLM developments & proposals|
|16:45 – 17:30|
|17:30 – 17:45||Wrap-up & Closing|
* Courtesy of Accellera, Cadence, Mentor a Siemens Business, and Synopsys
There are fivefor directly discussing of new ideas and suggestions within the SystemC community. You are invited to contribute during these sessions.
#1: SystemC AMS Update
Organizers: Einwich Karsten, COSEDA Technologies GmbH
The lightning talk will give an update of the SystemC AMS working group activities. The new features discussed for the next standard update will be presented. The goal is to gain feedback from the community.
In the second part proposals for the SystemC language standard from an AMS use case and SystemC AMS implementation perspective will be presented to initiate the discussion.
#2: SystemC Multi-language Requirements
Organizers: Martin Barnasconi, NXP; Faris Khundakjie, Intel; Alex Chudnovsky; Vitaly Yankelevich, Cadence; Warren Stapleton; Bryan Sniderman, AMD
The proposed talk will present the requirements and enhancements to apply the SystemC Library in the context of multi-language verification frameworks. The Accellera Multi-Language Verification Working Group (MLVWG) is currently working on a proof-of-concept which introduces and validates these enhancements to the SystemC library in such a multi-language verification framework. To align on the potential to standardize and implement such features in the SystemC standard and library, a technical discussion at the SystemC evolution day is suggested.
#3: Where Are We on CCI?
Organizer: Engblom Jakob, Intel
This session provides an update on the CCI standard and an opportunity for feedback from the audience. The CCI Configuration standard was released in June of 2018 – what is the current uptake? We want to hear from the audience about their experience so far! We will also discuss the direction of CCI for 2019.
#4: Functional Coverage for SystemC
Organizer: Dragos Dospinescu, AMIQ
Functional coverage lies at the core of functional verification as the primary metric that assesses the quality of the entire verification process. This notion of functional coverage can be extended from the scope of RTL verification to the verification of any type of application.
The Functional Coverage for SystemC (FC4SC) library provides mechanisms for functional coverage definition, collection and reporting that can be used in any application which is compliant with the C++ standard, starting with C++11. Because FC4SC is a header-only library and has no dependency on any third party library, it can be integrated with minimal effort into any application. In addition, the library provides an API that closely resembles functional coverage definition and usage defined by the IEEE 1800-2017 standard, facilitating the transition from SystemVerilog to FC4SC also allowing the possibility of developing tools for functional coverage conversion between the two. The library saves collected data in the UCIS format in order to be compatible with existing functional coverage tools provided by 3rd party vendors (e.g. Cadence, Mentor, Synopsys).
FC4SC use cases primarily involve (but are not limited to) measuring the level of exercise of SystemC models in order to track the features that are tested. This includes anything ranging from block level functional coverage, up to system level scenarios.
#5: TLM Developments & Proposals
Organizers: Joachim Geishauser, NXP; Ingo Feldner, Robert Bosch
This section will discuss different TLM developments, e.g. the application of TLM for serial interfaces, as well as a generic payload enhancement proposal.
After the technical sessions, an open discussion session will be used to summarize the next steps for further progressing within the relevant Accellera SystemC Working Groups by theon the session topics as well as additional opens brought up during the closing discussion. If you would like to become an Accellera member to participate in the working groups, information on how to join can be found at .
The event will take place in the Holiday Inn Munich City Hotel, Germany. Hotel details can be found at the DVCon Europe 2018 page (https://dvcon-europe.org/hotel-travel)
Registration is required, but free of charge. Seats are limited, so register soon!