Subject: Re: [sv-bc] Proposal for extern modules
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Feb 14 2003 - 10:28:12 PST
Good morning Karen, all;
Reading this proposal (between the lines), it appears that one would most likely do
the following (so their code would be synopsyzable.)
Write modules in this form:
% head -30 mod_a.vh
extern module a #(parameter size= 8, parameter type TP = logic[7:0])
(input [size:0] a, output TP b);
%
% head -20 mod_a.v
`include "mod_a.vh" // Include the port definitions of this module.
// here is module a
module a (.*);
...
They would instantiate modules and the file would look like:
% head -30 mod_top.v
`include "mod_top.vh" // Include the port definitions of top
// Now include the ports of the rest of the instantiated modules.
`include "mod_a.vh" // ports of module a
module top (.*);
...
a ia (
.me (my_con),
...
.*);
Is this the correct idea?
Downsides:
1. Now my port definitions are in a separate file - you have to have two files open
to figure out a module.
2. Every module (that is instantiated with .*) needs to have this include file...
Is there no way to allow the tools to read a module just to get the port definition?
You are effectively making the user do this work instead of the tools. This topic has
been discussed in other languages (software.)
Can a tool not have another option (like the library searching options) to specify
modules for port definition reading?
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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