Subject: Re: [sv-bc] Proposal for extern modules
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Fri Feb 14 2003 - 12:03:54 PST
Hi, Adam,
Thank you for reviewing my proposal.
In the proposal, note that the use of extern modules is not required, the
proposal merely allows their
declaration. It would be up to the tool to decide whether or not the
declaration was required.
For DC, if the user was willing and able to run analyze on both modules,
HDLC could fill
in the .* (I don't believe the netlist readers could; however). The issue
for HDLC arises when
the down modules come in from other paths, .db, .lib, or the netlist reader
for example, or when
it is too early in the design cycle to have all of the submodules defined.
Also note that the module declaration does not need to be implemented with
.*, that is merely
permitted. I could easily imagine an awk script that scans a library and
creates a header file from
modules declared in the library.
Extern module declarations may also be useful for tools wanting to provide
separate compilation
for compiled simulation performance. Again, in that case, more than the
interface of the down
module may not be known, so why require it's declaration?
Allowing extern modules provides a way for the user and tools to work
around these situations.
Karen
At 12:28 PM 2/14/03 -0600, Adam Krolnik wrote:
>Good morning Karen, all;
>
>
>Reading this proposal (between the lines), it appears that one would most
>likely do
>the following (so their code would be synopsyzable.)
>
>
>Write modules in this form:
>
>% head -30 mod_a.vh
>
> extern module a #(parameter size= 8, parameter type TP = logic[7:0])
> (input [size:0] a, output TP b);
>
>%
>
>% head -20 mod_a.v
>
>`include "mod_a.vh" // Include the port definitions of this module.
>// here is module a
>module a (.*);
>...
>
>
>They would instantiate modules and the file would look like:
>
>% head -30 mod_top.v
>
>`include "mod_top.vh" // Include the port definitions of top
>
>// Now include the ports of the rest of the instantiated modules.
>`include "mod_a.vh" // ports of module a
>
>module top (.*);
>...
>
>a ia (
> .me (my_con),
> ...
> .*);
>
>
>Is this the correct idea?
>
>Downsides:
>
> 1. Now my port definitions are in a separate file - you have to have
> two files open
> to figure out a module.
>
> 2. Every module (that is instantiated with .*) needs to have this
> include file...
>
>
>Is there no way to allow the tools to read a module just to get the port
>definition?
>You are effectively making the user do this work instead of the tools.
>This topic has
>been discussed in other languages (software.)
>
>Can a tool not have another option (like the library searching options) to
>specify
>modules for port definition reading?
>
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
>
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