Subject: [sv-bc] Ref ports documentation wrong or missing
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Aug 20 2003 - 10:59:30 PDT
Hi, All -
This is a follow-up to my email of a couple of days ago. I have not seen
any activity on this issue and don't want it to get dropped.
I found nothing to suggest that implicit ref-ports assigned in two separate
modules with continuous assignments and connected at a higher level had
behavior any different than last-assignment-wins, same as if they had been
procedural assignments to variables within the modules. This is what I
mentioned in the meeting.
Reference my email of 8/18 for more details.
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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