Subject: RE: [sv-bc] Ref ports documentation wrong or missing
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Aug 20 2003 - 11:17:38 PDT
Cliff,
See section 9.6 Continuous Assignments. It says:
" ... Variables can only be driven by one continuous assignment or one
primitive output. It shall be an error for a variable driven by a
continuous assignment or primitive output to have an initializer in the
declaration or any procedural assignment. See also Section 5.6."
So the same variable written to be 2 continuous assignments is an error.
The case you have is the same variable being written to inside an
interface by 2 assignments in 2 different places. I read the above as
making this erroneous.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
> Sent: Wednesday, August 20, 2003 2:00 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] Ref ports documentation wrong or missing
>
>
> Hi, All -
>
> This is a follow-up to my email of a couple of days ago. I
> have not seen
> any activity on this issue and don't want it to get dropped.
>
> I found nothing to suggest that implicit ref-ports assigned
> in two separate
> modules with continuous assignments and connected at a higher
> level had
> behavior any different than last-assignment-wins, same as if
> they had been
> procedural assignments to variables within the modules. This
> is what I
> mentioned in the meeting.
>
> Reference my email of 8/18 for more details.
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
>
>
>
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