Subject: Re: [sv-bc] Ref ports documentation wrong or missing
From: Dave Rich (David.Rich@synopsys.com)
Date: Wed Aug 20 2003 - 11:54:43 PDT
Cliff,
Sorry for not responding earlier. Darn day job :-)
ref ports are defined in section 18.8.1
— A ref port shall be connected to an equivalent variable data type.
References to the port variable shall be
treated as hierarchal references to the variable it is connected to in
its instantiation. This kind of port can
not be left unconnected.
Look at the following two illegal examples
module top;
bit a;
assign a = 0;
bot b1();
endmodule
module bot;
assign top.a = 1; // illegal assignment because there are now 2 CAs to top.a
endmodule
Same example with equivalent ref port
module top;
bit a;
assign a = 0;
bot b1(a);
endmodule
module bot (ref bit b);
assign b = 1; // illegal assignment because there are now 2 CAs to top.a
endmodule
Clifford E. Cummings wrote:
> Hi, All -
>
> This is a follow-up to my email of a couple of days ago. I have not
> seen any activity on this issue and don't want it to get dropped.
>
> I found nothing to suggest that implicit ref-ports assigned in two
> separate modules with continuous assignments and connected at a higher
> level had behavior any different than last-assignment-wins, same as if
> they had been procedural assignments to variables within the modules.
> This is what I mentioned in the meeting.
>
> Reference my email of 8/18 for more details.
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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