[sv-bc] RE: [sv-ec] Is instance constant allowed outside class?

Steven,

I don't think this was the reason. The initialization procedure has
nothing and should have nothing to do with the const'ness of a variable.
SystemVerilog has always allowed non-constant expressions in const
initializations.

The order of initialization problem exists for static variables, again
regardless of whether they are also const.

Dave

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Monday, April 05, 2010 10:34 AM
> To: shalom.bresticker@intel.com; spsaha@cal.interrasystems.com
> Cc: Rich, Dave; daniel.mlynek@aldec.com.pl; sv-ec@eda.org;
sv-bc@eda.org;
> bijoy@cal.interrasystems.com
> Subject: Re: [sv-ec] Is instance constant allowed outside class?
>
> At one point, I believe the initializers for const variables were
> required
> to be constant expressions (meaning elaboration-time constants). This
> served a useful purpose, as it prevented any simulation-time execution
> order
> dependencies from affecting the const variable values.
>
> At a later time, this rule was relaxed to allow other const variables
to
> appear in the initializers for const variables. When this happened,
it
> became pointless to restrict the expression at all. Allowing const
> variables (and hierarchical references to const variables) allowed all
> possible problems with order dependencies.
>
> I assume that you are seeing text that was left over from the older
> restriction. And implementors may be ignoring restrictions that serve
> no useful purpose.
>
> Steven Sharp
> sharp@cadence.com

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