[sv-bc] RE: [sv-ec] Is instance constant allowed outside class?

>SystemVerilog has always allowed non-constant expressions in const
>initializations.

I went back to the oldest version I could find, and it didn't require
constant expressions. So I guess my recollection was wrong.

But that leaves me at a loss to explain why the LRM places any restrictions
of constant-ness on const initializations. It says

"A static constant declared with the const keyword can be set to an
expression of literals, parameters, local parameters, genvars, enumerated
names, a constant function of these, or other constants."

It specifically says "or other constants", not "or variables". If it were
not intended to place any restrictions, it could have dispensed with this
list and just said "any expression".

Can you provide any plausible explanation for this pointless restriction
being in the LRM?

Steven Sharp
sharp@cadence.com

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