Re: [sv-bc] Non-ANSI port declaration without direction

I guess it's too late to complain, but what's the advantage to users in allowing
a port with no direction to default to inout? Where does the boost in productivity
come from? Rather than a design aid it just seems like a disabled error check.

Another feature that I can't complain about (though I will :-) is declaring
a port of an interface type without the 'interface' keyword. The parser
used to be able to catch common typos like this, but now we have to wait
until elaboration:

    module test(input x, ouput y);
    endmodule

If the 'interface' keyword were required for interface-type ports, then the parser
would be able to catch this error. This isn't such an onerous requirment for
the user -- in syntactic terms just think of 'interface' as another port direction
keyword.

Paul
----- Original Message -----
From: "Surya Pratik Saha" <spsaha@cal.interrasystems.com>
To: sv-bc@eda.org
Sent: Wednesday, April 21, 2010 10:42:47 AM
Subject: [sv-bc] Non-ANSI port declaration without direction

Hi,
As per SV 2009 LRM section 23.2.2.3 "Rules for determining port kind,
data type and direction", it is mentioned that "If the direction is
omitted, it shall default to inout.". May be it is implicitly applied
only to the ANSI style port declaration. But what is about this case in
non-ANSI style:

module (x);
    wire x;
endmodule

Is it not equivalent of :
module (x);
    inout wire x;
endmodule

Most of the standard simulator fail for the original case. But what is
the harm by passing the case considering the port as 'inout'?

-- 
Regards
Surya
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