[sv-bc] Non-ANSI port declaration without direction

Hi,
As per SV 2009 LRM section 23.2.2.3 "Rules for determining port kind,
data type and direction", it is mentioned that "If the direction is
omitted, it shall default to inout.". May be it is implicitly applied
only to the ANSI style port declaration. But what is about this case in
non-ANSI style:

module (x);
    wire x;
endmodule

Is it not equivalent of :
module (x);
    inout wire x;
endmodule

Most of the standard simulator fail for the original case. But what is
the harm by passing the case considering the port as 'inout'?

-- 
Regards
Surya
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.