RE: [sv-bc] Non-ANSI port declaration without direction

I've seen this problem before.
From analysing LRM I would say that :
- in 1800-2005 it was defined that inout direction is assumed for nonANSI
module header if no direction is defined
- in 1800-2009 you have to define explicitly port direction when using
nonANSI module header

DANiel

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Surya
Pratik Saha
Sent: Wednesday, April 21, 2010 4:43 PM
To: sv-bc@eda.org
Subject: [sv-bc] Non-ANSI port declaration without direction

Hi,
As per SV 2009 LRM section 23.2.2.3 "Rules for determining port kind, data
type and direction", it is mentioned that "If the direction is omitted, it
shall default to inout.". May be it is implicitly applied only to the ANSI
style port declaration. But what is about this case in non-ANSI style:

module (x);
    wire x;
endmodule

Is it not equivalent of :
module (x);
    inout wire x;
endmodule

Most of the standard simulator fail for the original case. But what is the
harm by passing the case considering the port as 'inout'?

--
Regards
Surya
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