[sv-bc] Query about bit-length of Context-Determined Expression

Hi,
     According to IEEE-Std1800-2009 LRM Section 11.6.1,

" *A context-determined expression is one where the bit length of the
expression is determined
by the bit length of the expression and by the fact that it is part of
another expression*.".

Does this imply that, the bit-length of the context-determined
expression is given by the
*/maximum/* of bit-lengths of the operand(s) and the context? Please
confirm.

Consider the example,

module A;
    reg [5:0] regA;
    reg [2:0] regB, regC;

    initial begin
        regA = 6'b0x0101; // 1
        regB = 3'b101; // 2
        regC = regA - regB; // 3
        $display("%b", regC);
    end
endmodule

In statement 3, if the bit-length of the context-determined binary
expression on RHS is
taken to be the maximum of bit-lengths of the operands and the context,
i.e. 6 (which is
the size of regA), then "regC" contains "xxx".
But if, the bit-length of the RHS is taken to be determined by the size
of the LHS
expression, i.e. 3, then value in "regC" must be "000".

Standard simulators give result "xxx".

Thanks and Regards,
Ishita.

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