[sv-bc] condition type expressions

Would it be useful to allow a conditional type expression like the following?

   parameter two_state = 1;
   parameter type t = two_state ? bit : logic;

You can get a similar effect using an extra level of hierarchy:

    generate
        if (two_state)
            sub #(bit) u1();
        else
            sub #(logic) u1();
    endgenerate

Paul

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