Re: [sv-bc] condition type expressions

I'm sure that there would be uses for it, yes. Obviously one
can make the type algebra much more interesting than it is
now by allowing such forms. But where does one draw the
line? Just defaults of parameter types? What about overrides
from parent modules? Conditional dimensions of an array? Conditional
fields of a struct? Conditional qualifications (signed/packed)?

I'm not terribly interested in going through such things unless
there are compelling reasons for which there aren't existing
solutions.

Gord.

Paul Graham wrote:
> Would it be useful to allow a conditional type expression like the following?
>
> parameter two_state = 1;
> parameter type t = two_state ? bit : logic;
>
> You can get a similar effect using an extra level of hierarchy:
>
> generate
> if (two_state)
> sub #(bit) u1();
> else
> sub #(logic) u1();
> endgenerate
>
> Paul
>

-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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