[sv-bc] Re: [sv-ac] Identifier usage before declaration in assertion

LRM 3.12 Compilation and elaboration addresses the elaboration.
Elaboration takes care of the variables being declared in the design. LRM: "Not
all syntax and semantics can be checked during
the compilation process."
Ben Cohen

On Sun, Jul 11, 2010 at 11:21 PM, Surya Pratik Saha <
spsaha@cal.interrasystems.com> wrote:

> Hi,
> For the following case:
> module top(input clk, input [3:0] iT, output [3:0] oT);
> assert property (@(posedge clk) (aa == 4'b0000)) ;
> reg [3:0] aa;
> always @(posedge clk)
> aa <= iT;
> assign oT = aa;
> endmodule // top
>
> All the standard simulators pass the case. Please note that 'aa' is used
> before it is declaration in the assertion statement. I could not find any
> text in the LRM regarding this. What is the reason of this?
>
> --
> Regards
> Surya
>
>
>
>
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