[sv-bc] Identifier usage before declaration in assertion

Hi,
For the following case:
module top(input clk, input [3:0] iT, output [3:0] oT);
   assert property (@(posedge clk) (aa == 4'b0000)) ;
   reg [3:0] aa;
   always @(posedge clk)
     aa <= iT;
   assign oT = aa;
endmodule // top

All the standard simulators pass the case. Please note that 'aa' is used
before it is declaration in the assertion statement. I could not find
any text in the LRM regarding this. What is the reason of this?

-- 
Regards
Surya
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