RE: [sv-bc] driving vriable from continous assignment and clocking block

The last sentence of Clause 14 is "It shall be illegal to write to a variable with a continuous assignment, a procedural continuous assignment, or
a primitive when that variable is associated with an output clockvar."

Shalom

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Daniel Mlynek
Sent: Monday, July 05, 2010 2:46 PM
To: 'sv-bc'
Subject: [sv-bc] driving vriable from continous assignment and clocking block

I cannot find in LRM rule saying if variable can be driven from continous assignment and in the same time can be clocking block output.
Is below code correct or not:

interface san_rt_query_if (input logic clk);
  logic rst_n;
  clocking cb @(posedge clk);
   inout rst_n; //rst_n is clocking block output
  endclocking : cb
endinterface: san_rt_query_if

module san_rt_rtl_top ();
  logic clk, rst_n;
  san_rt_query_if selected_query_if(.*);
  assign selected_query_if.rst_n = rst_n; //rst_n is continously assigned, should it be error as rst_n is already cb output???
endmodule : san_rt_rtl_top

DANiel

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