RE: [sv-bc] RE: [sv-ac] Identifier usage before declaration in assertion

The other complaint about Verilog is that it is too restrictive and does not allow you to do things you can do in VHDL...

Shalom

From: ben cohen [mailto:hdlcohen@gmail.com]
Sent: Tuesday, July 13, 2010 7:36 AM
To: Rich, Dave
Cc: Dhiraj Kumar Prasad; Eduard Cerny; Korchemny, Dmitry; Bresticker, Shalom; Surya Pratik Saha; sv-bc@eda.org; sv-ac@server.eda.org; Adhip Das
Subject: Re: [sv-bc] RE: [sv-ac] Identifier usage before declaration in assertion

<Just because tools "appear to support" an undocumented behavior is not enough reason to add that it to the LRM. >
<6.21 says, "A variable declaration shall precede any simple reference (non-hierarchical) to that variable.">
[Ben] From a methodology standpoint, I agree with what 6.21 states. In fact, VHDL requires that in an architecture, all signals must be declared before the block of the architecture. It's a good discipline, and I would not like to break it. One of the complaints about Verilog was that it was too loose of a language, that allowed almost anything with little regards to discipline.
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