RE: [sv-bc] RE: [sv-ac] Identifier usage before declaration in assertion

I confirm that.

Shalom

From: Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com]
Sent: Tuesday, July 13, 2010 7:09 AM
To: Bresticker, Shalom
Cc: Rich, Dave; Dhiraj Kumar Prasad; Eduard Cerny; Korchemny, Dmitry; ben@systemverilog.us; sv-bc@eda.org; sv-ac@server.eda.org; Adhip Das
Subject: Re: [sv-bc] RE: [sv-ac] Identifier usage before declaration in assertion

Hi Shalom,
Dhiraj's example did not go through all standard simulators. But, the example I showed (concurrent assertion) indeed passed by all standard simulators.

Regards

Surya

On Sun, Jul 11, 2010 at 11:21 PM, Surya Pratik Saha <spsaha@cal.interrasystems.com<mailto:spsaha@cal.interrasystems.com>> wrote:

Hi,
For the following case:
module top(input clk, input [3:0] iT, output [3:0] oT);
 assert property (@(posedge clk) (aa == 4'b0000)) ;
 reg [3:0] aa;
 always @(posedge clk)
   aa <= iT;
 assign oT = aa;
endmodule // top

All the standard simulators pass the case. Please note that 'aa' is used before it is declaration in the assertion statement. I could not find any text in the LRM regarding this. What is the reason of this?

--
Regards
Surya
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