[sv-bc] FW: Proposal: Reconciliation of SystemVerilog BNF with 5 recent Verilog errata fixes

Subject: [sv-bc] FW: Proposal: Reconciliation of SystemVerilog BNF with 5 recent Verilog errata fixes
From: David W. Smith (david.smith@synopsys.com)
Date: Mon Sep 08 2003 - 10:15:57 PDT

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Greetings,

Brad sent the attached proposal for making some BNF errata fixes to
SystemVerilog based on recent Verilog errata changes. These have been posted
as LRM-18 on www.eda.org/sv.

Regards
David

David W. Smith
Synopsys Scientist

Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124

Voice: 503.547.6467
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FAX: 503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com

-----Original Message-----
From: Brad Pierce [mailto:bpierce@Synopsys.COM]
Sent: Friday, September 05, 2003 4:54 PM
To: David W. Smith
Subject: RE: Proposal: Reconciliation of SystemVerilog BNF with 5 recent
Verilog errata fixes

David,

I forgot to make a pair of '=' red. Attached is the corrected version.

-- Brad

• text/html attachment: BNF_reconciliation.htm

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