Hi Steve.
Shift registers often are loaded in parallel (and I think
read out in parallel). Why should the SV language exclude
this possibility just because of operation of a register
file as a FIFO?
-- John Michael Williams jwill@BasicISP.net -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jul 23 09:10:06 2010
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