Hi Steve.
Shift registers often are loaded in parallel (and I think
read out in parallel). Why should the SV language exclude
this possibility just because of operation of a register
file as a FIFO?
For example, on putting to sleep a block containing a FIFO,
one might want to offload it as a RAM; then, on wakeup for
a low-power mode, one might want to load it back up
without having to execute the FIFO write process. If
the FIFO happened to be involved in the sleep/wakeup,
one might want to wake it up by reloading it in some
different data-state than the original.
I think this idea is trying to make the compiler smarter than
a designer; actually, a compiler never should be smarter
than a designer -- only more attentive to detail.
-- John Michael Williams jwill@BasicISP.net -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jul 23 09:14:59 2010
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