RE: [sv-bc] Query related with property port list.

I don't think arrays of properties are defined in the LRM.
For example, I don't think there is a way to select an individual property from the array.
For example, the BNF of property_instance is

property_instance ::=
        ps_or_hierarchical_property_identifier [ ( [ property_list_of_arguments ] ) ]

This does not allow you to follow the property identifier with an index.

As usual, not everything that is technically possible to construct according to the BNF is actually legal.

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Dhiraj Kumar Prasad
> Sent: Monday, December 13, 2010 11:51 AM
> To: sv-bc@server.eda.org
> Cc: Kakoli Bhattacharya; Dhiraj Kumar Prasad
> Subject: [sv-bc] Query related with property port list.
>
> Hello,
>
> I have a query related with property_port_list.
>
> According to LRM 1800-2009,section 16.13 BNF
>
> property_port_list ::=
> property_port_item {, property_port_item}
>
> property_port_item ::=
> { attribute_instance } [ local [ property_lvar_port_direction ] ]
> property_formal_type
> port_identifier {variable_dimension} [ = property_actual_arg ]
>
> For the given testcase
>
> module mod1(input clk);
>
> property p1(bit b1[1:0]);
> //property p1(property b1[1:0]);
> @(posedge clk) b1[0];
> endproperty
>
> property p2;
> @(posedge clk) 1;
> endproperty
>
> always@(*)
> begin
> // as2 : assert property (p1('{default : p2}));
> as1 : assert property (p1('{default : 1'b1})); //failing for this
> end
> endmodule
>
> When the property port contain property as property_formal_type with
> variable dimension than most of the tool are
> showing error for assert "as2" but when it's bit,some of the tool are
> passing.
>
> I would like to know if the testcase is wrong(although supported by
> BNF).
>
> Regards,
> dhiRAj

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