Re: [sv-bc] Generate with multiple begins

Hi Brad.

I guess that you are suggesting that loop generates
should have different rules than conditional generates?

On 01/10/2011 08:09 AM, Paul Graham wrote:
> Brad,
>
> Gotcha! Vhdl-2008 now has generate-else clauses :-)
>
> Paul
> ----- Original Message -----
> From: "Brad Pierce"<brad_pierce@acm.org>
> To: sv-bc@eda.org
> Sent: Monday, January 10, 2011 11:00:35 AM
> Subject: Re: [sv-bc] Generate with multiple begins
>
> Verilog would have been wise to copy VHDL generate, but instead
> Verilog went its own expansive way. Arguing from analogy with VHDL now
> is not much of a guide. If it is to be a guide, then let's start by
> prohibiting generate 'else' clauses.
>
> -- Brad
...

-- 
      John Michael Williams
      Senior Adjunct Faculty
Silicon Valley Technical Institute
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