RE: [sv-bc] Generate with multiple begins

As I remember, at least part of the reasoning went like this:

1. A begin-end at the top level of the generate region did not appear to be useful.

2. In Verilog-2001, it did not create a new hierarchy scope. In Verilog-2005, it would have done so. That would have been confusing.

3. So it was decided not to allow it at the top level of the generate region. Once that was decided, it seemed consistent and unharmful to disallow this elsewhere as well. It also made the BNF simpler.

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Steven Sharp
> Sent: Tuesday, January 11, 2011 1:22 AM
> To: Paul Graham
> Cc: SV-BC; Wilson Snyder; Gordon Vreugdenhil
> Subject: RE: [sv-bc] Generate with multiple begins
>
>
>
> -----Original Message-----
> From: Paul Graham [mailto:pgraham@oasys-ds.com]
>
> >If you allow a begin/end block by itself in a concurrent scope, then
> you might as well allow nesting.
>
> Since begin/end blocks aren't allowed by themselves in concurrent
> scopes, this argument doesn't apply.
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