RE: [sv-bc] Generate with multiple begins

Hi,
While fixing a Verilog-2001 code into SV standard, I just found one more example where toplevel labeled begin-ends are necessary:
            If you want to re-use the same case statement code in several different generate blocks within the same module,
            You must use toplevel labels (SEL1, SEL2) else you will get duplicated labels (CASEOR) in this example :

=======================================

  generate

     // mandatory label

begin:SEL1

    case(SELECTOR1)

       4'd1: begin:CASEOR

         m_or g52 ();

       end // CASEOR

       4'd2: begin:CASEOR

         m_or g52();

       end

       4'd3: begin:CASEOR

         m_or g52 ();

       end

       4'd4: begin:CASEOR

         m_or g52 ();

       end

     endcase

     end:SEL1

   endgenerate

   // ------------------------------------------------

              generate

     // mandatory label

begin:SEL2

    case(SELECTOR2)

       4'd1: begin:CASEOR

         m_or g52 ();

       end // CASEOR

       4'd2: begin:CASEOR

         m_or g52();

       end

       4'd3: begin:CASEOR

         m_or g52 ();

       end

       4'd4: begin:CASEOR

         m_or g52 ();

       end

     endcase

     end:SEL2

   endgenerate

   // ------------------------------------------------

Regards,
Gal Vardi

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