[sv-bc] Implicit net declaration for explicit port

Hi,
I got a design like:

module top(input .p(x));
     assign x = 1;
endmodule

As per LRM, 'x' needs to be explicitly declared. But by the continuous
assignment, is 'x' allowed to be declared implicitly for this case? Some
standard tools pass the case. Please let me know your view.

-- 
Regards
Surya
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.