RE: [sv-bc] Implicit net declaration for explicit port

I don't think the LRM says that x needs to be explicitly declared.

Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Surya Pratik Saha
> Sent: Wednesday, January 26, 2011 5:14 AM
> To: sv-bc@eda.org
> Cc: Adhip Das
> Subject: [sv-bc] Implicit net declaration for explicit port
>
> Hi,
> I got a design like:
>
> module top(input .p(x));
> assign x = 1;
> endmodule
>
> As per LRM, 'x' needs to be explicitly declared. But by the continuous
> assignment, is 'x' allowed to be declared implicitly for this case?
> Some
> standard tools pass the case. Please let me know your view.
>
> --
> Regards
> Surya
>
>
>
>
> --
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