RE: [sv-bc] Generate with multiple begins

1. I don't think there is any real distinction between "toplevels" and "bares". A "toplevel" is just a "bare" at the top level.

The 2001 standard allowed begin-ends without an associated generate construct, which is presumably what you are calling "bares". It also had some problems that made it impractical to implement as written. Most of these problems were fixed in the 2005 standard by introducing a scope or level of hierarchy for each generate construct. To simplify use, the user was no longer required to declare these scopes explicitly using named begin-ends. The begin-end just became a convenient place to hang a name for the scope that was already being created, rather than creating a scope. "Bare" begin-ends that were not associated with any generate construct were dropped at the same time.

The "bare" begin-ends didn't cause any problems. I think hey were just seen as unnecessary. Various tools probably allowed them anyway, to maintain some level of backward compatibility with the 2001 version of generates.

Whether they are allowed can be seen from the BNF for the language grammar, which is more precise than the text description.

This isn't a matter of two different working versions of the language. The 2001 version was flawed, and the 2005 version was intended to replace it completely.

2. I don't understand the uses you are describing here.
   Toplevels: There is no need to use a begin-end to have multiple if/case/for statements within a generate-endgenerate
      (which is called a generate region, not a generate block, which is something else). In fact, there is no need to have
     generate-endgenerate at all in the 2005 standard. Begin-end is not needed at the top level.
   Bares: A begin-end is allowed directly inside of a generate-if/case, if you need to have multiple generate-constructs inside.
      These are not bare. You don't need more than one begin-end inside, so this satisfies the need.

As far as the naming convention, the standard already provides a complete naming convention for the unnamed begin-end blocks that it allows. This should be used by all tools. If tools are allowing nonstandard "bare" begin-end blocks, they may end up varying in how they treat the naming. Appropriate names can be extrapolated from the existing rules, but there may be differences of opinion in how to generalize them. It is also possible that you are seeing tools that have ignored the standard naming convention.

________________________________
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Gal Vardi
Sent: Thursday, February 24, 2011 3:09 AM
To: SV-BC
Subject: RE: [sv-bc] Generate with multiple begins

Hi,

We just ran into this limitation with one of the synthesis tools.

In the plain Verilog-2001 code we currently use, there are begin-end at the toplevel, and "bare" begin-ends inside generate. No tool complained until Jan 2011 (and we usually check a wide range of them from different vendors)

1. Can I understand exactly which standard allows each of "toplevels" and "bares", and which standard forbids. It is not straightforward from the text in the standards.

2. If it is not too late to argue, I'd like to humbly add my personal opinion:

            Both the begin-end at the toplevel and the bare ones inside are useful:

Toplevels: if you have couple of if/case/for statements within a single generate block

Bares: within a hierarchical if/then/else or hierarchical case statements.

I also like the orthogonally raised by Paul Graham. Orthogonally for a designer means simplicity: You can place a [named] begin-end wherever you like, it will never be an error.

A related issue is the naming convention of the un-named begin-end blocks, and how to keep hierarchical naming consistency between different tools, from Equivalence to SDC format.

I prepared a suggestion regarding that issue and can post it if there is a related thread in this workgroup or else where you may suggest.

Regards,

Gal Vardi

________________________________
Gal Vardi, Marvell Israel - Staff Silicon Integration Engineer
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