RE: [sv-bc] Use before definition

I agree with Greg that the presence of the identifier in the non-ANSI-style port list does not constitute a definition. I have verified that Verilog-XL produces an error, so the use in the port list was never considered to be a definition.

Prior to the 2005 LRM, the use in the continuous assignment would have been a reference to an undeclared identifier. After the 2005 LRM, an undeclared identifier on the LHS of a continuous assignment creates an implicit net declaration for blah. I would then expect an error for the later explicit declaration of blah. Greg suggests that this might be accepted by some tools as long as the explicit declaration matched the previous implicit declaration.

Since Verilog-XL does not support this 2005 feature, I tried replacing the continuous assignment with a connection to a gate terminal, which would produce an implicit net declaration in Verilog-XL as well. It produced the same error for the use, and then produced an additional error for the duplicate declaration. This indicates that an explicit re-declaration of an implicitly declared net was illegal in the tool that the standard was based upon. This supports Greg's personal opinion (and mine) that this should be illegal.

________________________________
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Greg Jaxon
Sent: Tuesday, March 15, 2011 5:39 PM
To: sv-bc@eda.org
Subject: Re: [sv-bc] Use before definition

On 3/13/2011 4:17 AM, Bisht, Laurence S wrote:
Hey Sv-bc,
I wonder about the following:

module foo (blah);

assign blah = 1'b0; // Usage

output blah;

wire blah; // Definition

endmodule
Is this code legal?
Thanks,
Laurence

If the `default_nettype is not "wire" (which is its default), the code should report an error.

The first two lines correspond to a typical "implicit net" style of use.
Whether subsequent explicit declaration is legal does not seem to be discussed in the standard.
Here the declaration looks redundant, and one synthesis tool I tried accepts it with just a
warning - but it also accepted the code when I set `default_nettype triand
which isn't strictly redundant.

Since I can imagine lots of ways for this to come out wrong in a compiler, I'd suggest
(personal opinion only) that implicit nets should not permit any additional explicit property declarations.
This is the sort of consistency issue that lint tools should excel at detecting - whether
production compilers need such checks may be a matter of market preference.

Codes that rely on implicit nets, probably need something stronger than lint to stay out of trouble...
Any pair of close-but-no-cigar spellings might be a missed connection.

Greg Jaxon
Disclaimer: no clues here about voting positions of, nor product features delivered by, my employer...

--
This message has been scanned for viruses and
dangerous content by MailScanner<http://www.mailscanner.info/>, and is
believed to be clean.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.