On 3/13/2011 4:17 AM, Bisht, Laurence S wrote:
Hey
Sv-bc,
I
wonder about the following:
module foo (blah);
assign blah = 1’b0; // Usage
output blah;
wire blah; // Definition
endmodule
Is
this code legal?
Thanks,
Laurence
If the
`default_nettype is not "
wire"
(which is its default), the code should report an error.
The first two lines correspond to a typical "implicit net" style of
use.
Whether subsequent explicit declaration is legal does not seem to be
discussed in the standard.
Here the declaration looks redundant, and one synthesis tool I tried
accepts it with just a
warning - but it also accepted the code when I set
`default_nettype
triand
which isn't strictly redundant.
Since I can imagine lots of ways for this to come out wrong in a
compiler, I'd suggest
(personal opinion only) that implicit nets should not permit any
additional explicit property declarations.
This is the sort of consistency issue that lint tools should excel
at detecting - whether
production compilers need such checks may be a matter of market
preference.
Codes that rely on implicit nets, probably need something stronger
than lint to stay out of trouble...
Any pair of close-but-no-cigar spellings might be a missed
connection.
Greg Jaxon
Disclaimer: no clues here about voting positions of, nor product
features delivered by, my employer...
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Received on Tue Mar 15 14:39:17 2011