[sv-bc] 4-state or 2-state expression types

SV has defined the ability to take the "type" of an expression without
evaluating
the expression. In some circumstances, there is insufficient
description in the
LRM about exactly what constitutes the type of an expression versus the
values induced by the expression. 11.3.4 has the following wording:

     Operators may be applied to 2-state values or to a mixture of
2-state and
     4-state values. The result is the same as if all values were
treated as 4-state
     values. In most cases, if all operands are 2-state, the result is
in the 2-state
     value set.

This doesn't really say that the *type* of the expression becomes 4-state
just that the result is in the 4-state value set.

So, consider the following:
      bit [7:0] a;
      int i;

      type (a/0) v1;
      type (a[7:6]) v2;
      type (a[10:7]) v3;
      type (a[i+:4]) v4;

What is the type of each variable? Does the "partially out of range" result
of v3 impact the type (i.e. is it 4-state due to the "x" bits)? If v3
is 4-state,
what about v4? Is it 4-state due to the *possibility* of an out-of-bounds
select (remember that the expression is not evaluated)?

I'm not sure that I'd want to say that *every* select induces a 4-state
type, but if we don't, then we have issues with indexed selects, etc.

The question is not academic as the user expectations of induced 2-state
types interact with the behavior of conditionals, etc.

Gord.

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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