RE: [sv-bc] 4-state or 2-state expression types

My intent for the wording in 11.3.4 was that if you applied an operator, all operands were converted to 4-state and the result was 4-state (though implementations would be free to optimize by doing 2-state operations if all operands were 2-state and the operator could not produce a 4-state result).

So the type of v1 would be 4-state. It would be 4-state even if it were type(a+1), which cannot produce x or z.

But the part selects are not officially operators.

For a bit-select of a 2-state vector, I believe an out-of-range result is specified to be "the default uninitialized value" for an element of the vector. That would be 0 rather than X.

I guess I had assumed that part-selects worked the same way, producing 0 for out-of-range bits of a 2-state vector. But perhaps they were not generalized in the same way that bit-selects were, and still explicitly refer to X.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Gordon Vreugdenhil
Sent: Tuesday, March 22, 2011 4:29 PM
To: sv-bc
Subject: [sv-bc] 4-state or 2-state expression types

SV has defined the ability to take the "type" of an expression without evaluating the expression. In some circumstances, there is insufficient description in the LRM about exactly what constitutes the type of an expression versus the values induced by the expression. 11.3.4 has the following wording:

     Operators may be applied to 2-state values or to a mixture of 2-state and
     4-state values. The result is the same as if all values were treated as 4-state
     values. In most cases, if all operands are 2-state, the result is in the 2-state
     value set.

This doesn't really say that the *type* of the expression becomes 4-state just that the result is in the 4-state value set.

So, consider the following:
      bit [7:0] a;
      int i;

      type (a/0) v1;
      type (a[7:6]) v2;
      type (a[10:7]) v3;
      type (a[i+:4]) v4;

What is the type of each variable? Does the "partially out of range" result of v3 impact the type (i.e. is it 4-state due to the "x" bits)? If v3 is 4-state, what about v4? Is it 4-state due to the *possibility* of an out-of-bounds select (remember that the expression is not evaluated)?

I'm not sure that I'd want to say that *every* select induces a 4-state type, but if we don't, then we have issues with indexed selects, etc.

The question is not academic as the user expectations of induced 2-state types interact with the behavior of conditionals, etc.

Gord.

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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com
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