[sv-bc] RE: IEEE P1800 Draft 6 (Preliminary) Download ready for review

SV-AC found an editorial error a week ago, I though Stu knew about it.

In Syntax 23-5 on page 673, Footnote 4 says,

"If the bind_target_scope is an interface_identifier or the bind_target_instance is an interface_instance_identifier,
then the bind_instantiation shall be an interface_instantiation."

It should say,

"If the bind_target_scope is an interface_identifier or the bind_target_instance is an interface_instance_identifier,
then the bind_instantiation shall be an interface_instantiation or a checker_instantiation."

as in Syntax 23-9 and as in A.10.

The addition of "or a checker_instantiation" was part of Mantis 1900 and was performed in two of the three places where the footnote appears.
The third place was missed, probably because the location reference appearing in Mantis 1900 was incorrect (maybe referring to an out of date version of the LRM draft).

In any case, it should be corrected now. The normative version of the footnote is that appearing in A.10.
The other places are excerpts from Annex A and should conform to the text there.

In addition, in Example 2 on page 744, "endpackage" should be bold.

Thanks,
Shalom

From: owner-sv-xc@eda.org [mailto:owner-sv-xc@eda.org] On Behalf Of Brophy, Dennis
Sent: Friday, August 17, 2012 21:41
To: IEEE P1800 Working Group
Cc: sv-xc@eda.org; sv-bc@eda.org; sv-ec@eda.org; sv-cc@eda.org; sv-ac@eda.org
Subject: RE: IEEE P1800 Draft 6 (Preliminary) Download ready for review

All,

Preliminary 2 of Draft 6 of the P1800 SystemVerilog-2012 standard is now available for download at https://mentor.ieee.org/1800/dcn/12/1800-12-0004-00-DRFT-ieee-p1800-systemverilog-d6-prelim-2.pdf.

Stu indicates a few minor editor errors were noted during the review of the preliminary draft of P1800/D6. He has fixed those mistakes.

-Dennis

From: Rich, Dave
Sent: Tuesday, August 14, 2012 5:20 PM
To: Brophy, Dennis; IEEE P1800 Working Group
Cc: sv-xc@eda.org<mailto:sv-xc@eda.org>; sv-bc@eda.org<mailto:sv-bc@eda.org>; sv-ec@eda.org<mailto:sv-ec@eda.org>; sv-cc@eda.org<mailto:sv-cc@eda.org>; sv-ac@eda.org<mailto:sv-ac@eda.org>
Subject: RE: IEEE P1800 Draft 6 (Preliminary) Download ready for review

Thanks to all of you who have reviewed this draft already.

We would really appreciate if the rest of you could get your comments in as soon as possible. We would like to get another draft out with the comments already integrated with enough time to review for the August 23rd Working Group meeting.

Dave
Mentor Graphics

From: owner-sv-xc@eda.org<mailto:owner-sv-xc@eda.org> [mailto:owner-sv-xc@eda.org]<mailto:[mailto:owner-sv-xc@eda.org]> On Behalf Of Rich, Dave
Sent: Thursday, August 09, 2012 3:55 PM
To: Brophy, Dennis; IEEE P1800 Working Group
Cc: sv-xc@eda.org<mailto:sv-xc@eda.org>; sv-bc@eda.org<mailto:sv-bc@eda.org>; sv-ec@eda.org<mailto:sv-ec@eda.org>; sv-cc@eda.org<mailto:sv-cc@eda.org>; sv-ac@eda.org<mailto:sv-ac@eda.org>
Subject: RE: IEEE P1800 Draft 6 (Preliminary) Download ready for review

Comments on this draft are due by August 21st.

People with assigned mantis items that have been marked completed should either close the mantis item, or send it back to the editor state if they find problems with the implementation of their changes.

Dave
Mentor Graphics

From: owner-ieee1800@eda.org<mailto:owner-ieee1800@eda.org> [mailto:owner-ieee1800@eda.org]<mailto:[mailto:owner-ieee1800@eda.org]> On Behalf Of Brophy, Dennis
Sent: Thursday, August 09, 2012 9:31 AM
To: IEEE P1800 Working Group
Subject: [P1800] IEEE P1800 Draft 6 (Preliminary) Download

All,

As a follow-up to the meeting today, the preliminary Draft 6 of the SystemVerilog standard has been uploaded to the mentor.ieee.org site. You can find it here: https://mentor.ieee.org/1800/dcn/12/1800-12-0003-00-DRFT-ieee-p1800-systemverilog-d6-prelim.pdf. (Login required.)

This preliminary draft is for Working Group and Ballot Resolution Committee review prior to release to the ballot pool for a ballot recirculation.

-Dennis

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