A synthesis tool I have supports always procedures in interfaces. Regards, Shalom From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Surya Pratik Saha Sent: Saturday, October 20, 2012 10:56 To: sv-bc@eda.org Subject: [sv-bc] Is usage of procedural blocks in Interfaces synthesizable Hi, As per the LRM, we can use procedural blocks in Interface. Conceptually that helps for design verification. But it is not clear whether it is synthesizable or not. Can someone help me on this? Regards Surya This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. -- This message has been scanned for viruses and dangerous content by MailScanner<http://www.mailscanner.info/>, and is believed to be clean. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Oct 21 03:05:31 2012
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