RE: [sv-bc] modport expression

There are issues with the description of modport expressions in the LRM, but I think the LRM is clear that the expression must be legal as a normal port high conn for a normal port of that direction.

Are there any restrictions on what variables or nets can be in a modport expressions? Can you use hierarchical references? Can you include variables from packages? Since all of those are legal for some kinds of module port high cons, apparently they are legal in modport expressions.

The most serious unresolved question in my mind is related to the text: “The self-determined type of the port expression becomes the type for the port.”

Self-determined data type is a well defined concept in the LRM, but what about the net type?  There is no concept of self-determined net type that I know of LRM and it is not clear how it could be defined.  Does this mean that all modport expression ports are variable ports?  This would mean that the inout direction would be illegal for modport expression ports.

What about the case where the modport expression is omitted? What type of port gets created in that case?

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Wednesday, November 21, 2012 7:32 AM
To: Daniel Mlynek; sv-bc@eda.org
Subject: RE: [sv-bc] modport expression

I would say that the sentence means,

"A modport expression is a way to allow such items as elements of arrays and structures, etc., to be included in a modport list, that would otherwise not be allowed to appear."

That is, the intent is,

"  - all kinds of expression on inputs and LHS expresion for other direction"
And about

"    input  .p1(i+j),"
the LRM says,

"The port expression shall resolve to a legal expression for type of module port (see 23.3.3). In the example above, the Q port could not be an output or inout because the port expression is a constant."

Regards,
Shalom


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Daniel Mlynek
Sent: Wednesday, November 21, 2012 13:44
To: sv-bc@eda.org
Subject: [sv-bc] modport expression

LRM says:
"A modport expression allows elements of arrays and structures, concatenations of elements, and assignment pattern expressions of elements declared in an interface to be includedin a modport list. This modport expression is explicitly named with a port identifier, visible only through the modport connection"

On the other handLRM explicitly do not forbid other kinds of expression and  in BNF you can find:
modport_simple_port ::=
   port_identifier
   | .port_identifier ([ expression ] )

My question is what is the LRM intention  - what should be allowed in modport expression:
  - all kinds of expression on inputs and LHS expresion for other direction
  - expression listed in 1st quotation above - item select, member select, concatenation and APE for all directions (input, output, ref , inout)

For input modport having expression not allowed on LHS of assignment can somehow work:
interface  iface;
  int i,j;
  modport mpi (
    input  .p1(i+j),
  );
endinterface




DANiel

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