RE: [sv-bc] modport expression

Mark,

The modport expression is a form of port declaration, not a port connection.
It declares a sort of alias.
It is similar to what is described in 23.2.2.1 for module port expressions:

"The port reference for each port in the list_of_ports in the module header can be one of the following:
— A simple identifier or escaped identifier
— A bit-select of a vector declared within the module
— A part-select of a vector declared within the module
— A concatenation of any of the above"

(This text goes back to Verilog-1995, so it does not mention newer types.)

"The port expression is optional because ports can be defined that do not connect to anything internal to the module. Once a port has been defined, there shall not be another port definition with this same name."

"The first type of module port, with only a port_expression, is an implicit port.
The second type is the explicit port. This explicitly specifies the port_identifier used for connecting module instance ports by name (see 23.3.2.2) and the port_expression that contains identifiers declared inside the module as described below. "

So it should only be able to reference identifiers declared within the interface, just like hierarchical references and package variables cannot be module ports.

Regarding "self-determined type of the port expression", this is again copied from the language describing named port expressions.

The issues you brought up are mentioned to some extent in Manti 1572 and 3607 with respect to module ports.

With respect to modport expression omitted, the LRM says with respect to both modport and module port expressions, "The port expression is optional because ports can be defined that do not connect to anything internal to the port." So I understand that essentially it declares a null port.

Regards,
Shalom

From: Mark Hartoog [mailto:Mark.Hartoog@synopsys.com]
Sent: Wednesday, November 21, 2012 20:56
To: Bresticker, Shalom; Daniel Mlynek; sv-bc@eda.org
Subject: RE: [sv-bc] modport expression

There are issues with the description of modport expressions in the LRM, but I think the LRM is clear that the expression must be legal as a normal port high conn for a normal port of that direction.

Are there any restrictions on what variables or nets can be in a modport expressions? Can you use hierarchical references? Can you include variables from packages? Since all of those are legal for some kinds of module port high cons, apparently they are legal in modport expressions.

The most serious unresolved question in my mind is related to the text: “The self-determined type of the port expression becomes the type for the port.”

Self-determined data type is a well defined concept in the LRM, but what about the net type?  There is no concept of self-determined net type that I know of LRM and it is not clear how it could be defined.  Does this mean that all modport expression ports are variable ports?  This would mean that the inout direction would be illegal for modport expression ports.

What about the case where the modport expression is omitted? What type of port gets created in that case?
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.