Re: [sv-bc] dotted names and interfaces

Mark writes in http://www.eda.org/sv-bc/hm/11419.html

"To allow variable index to an interface port array, we would have to
require that all elements of the array are identical. ... Defparams
can lead to “ip[i].a” having different width for different values of
‘I’."

That defparam loophole also subverts the homogeneity even of Verilog
arrays of module instances, and is a reason why variable indexing of
them is also disallowed.

What does that defparam loophole buy us? Normally an array would just
be a mapping from an index domain to a data domain, and the data
domain would have a well-defined data type.

Why not purge 'defparam' from the language? Those users who want it
can stick with SV12.

-- Brad

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.