[sv-bc] Re: [sv-ac] FW: DAC Presentation of SV-2012 Enhancements - Cliff requests your input

Cliff,
1) On assertions, 1800'2012 clarified vacuity for many of the properties,
including the one for the *implies* operator, which was poorly defined.
2) The SV "checker" was completely revamped and is more useful for
simulation and formal verification.
As a general comments, I would like to see vendors implement those
changes.  Some are doing a better job at adopting the features of 1800'09
and even touching on 1800'12.
Ben Cohen
systemverilog.us
On Wed, May 29, 2013 at 10:50 AM, Bresticker, Shalom <
shalom.bresticker@intel.com> wrote:

>  Hi,****
>
> Cliff Cummings asked me to forward this.****
>
> Shalom****
>
> *From:* Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
> *Sent:* Wednesday, May 29, 2013 20:46
> *To:* Bresticker, Shalom
> *Subject:* DAC Presentation of SV-2012 Enhancements - Cliff requests your
> input****
>
> ** **
>
> Hi, All -****
>
>  ****
>
> I have been asked to give a short SystemVerilog-2012 update presentation
> at DAC. Stu Sutherland has already done a nice update last year at DAC but
> I would like to take a slightly different approach while sill acknowledging
> and referencing his DAC presentation.****
>
>  ****
>
> I would like to gather input from as many SystemVerilog-2012 committee
> members as a I can regarding your favorite SystemVerilog-2012 enhancements.
> I would suggest that you email me with your five favorite enhancements
> (feel free to send fewer or more than five favorites).****
>
>  ****
>
> Everyone that sends me a small list of favorites will be acknowledged and
> thanked in my presentation, which will eventually go into the public domain
> and will also be posted on my web page. ****
>
>  ****
>
> Time is short! All I need is a list of your favorite enhancements,
> preferably by the end of day on Friday, but you get extra credit for the
> following:****
>
> (1) Why each enhancement is on your favorites list.****
>
> (2) Any examples that show why the enhancement is cool!****
>
> (3) Reference to specific section numbers of the IEEE 1800-2012 LRM.****
>
>  ****
>
> This is your chance to highlight enhancements that you as a committee
> member felt was important to the Design and Verification community.****
>
>  ****
>
> Thanks in advance for you short (or extended) feedback.****
>
>  ****
>
> If anybody has a complete list of the enhancements that was compiled
> separate from Stu's list, you get double-extra credit!****
>
>  ****
>
> Regards - Cliff****
>
> --
> Cliff Cummings - Sunburst Design, Inc. 1639 E. 1320 S., Provo, UT 84606 -
> 801-960-1996- cliffc@sunburst-design.com / www.sunburst-design.com World
> Class Verilog, SystemVerilog & OVM/UVM Training****
>
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