[sv-bc] uniszed unbased literal in a concatenation

Hi, Consider this code:

      module test1;

      wire [2:0] w1;
      wire [3:0] w ;

      assign w = {'0, w1};

      endmodule

Is this concatenation legal because '0 is 1 bit wide in a self-determined context, or is it illegal because it is an unsized constant in a concatenation?

I tend toward the first interpretation, but I see that some tools accept it and some do not.

Thanks,
Shalom

Shalom Bresticker
Intel, Networking Division DA, Jerusalem, Israel
+972  2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker



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