[sv-bc] RE: uniszed unbased literal in a concatenation

Hi Shalom,

I think it's legal, and 1-bit wide, but the designer probably thinks it means to fill out with 0's to the width of the LHS, that is, the same as

        assign w = w1;

except suppressing any warnings about the widths not matching.

-- Brad

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Monday, October 07, 2013 8:42 AM
To: SV_BC List
Subject: [sv-bc] uniszed unbased literal in a concatenation

Hi, Consider this code:

module test1;

wire [2:0] w1;
wire [3:0] w ;

assign w = {'0, w1};

endmodule

Is this concatenation legal because '0 is 1 bit wide in a self-determined context, or is it illegal because it is an unsized constant in a concatenation?

I tend toward the first interpretation, but I see that some tools accept it and some do not.

Thanks,
Shalom

Shalom Bresticker
Intel, Networking Division DA, Jerusalem, Israel
+972  2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker




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