Re: [sv-bc] Modport definitions

Yes, that was (one of) Francoise's question.

Unlike V95 style, SystemVerilog port and modport expressions require you
to use a new port_name instead of just using the expression in the port
list.

Dave

Adam Krolnik wrote:

>
>
> Good morning;
>
>
> Is it possible to declare a port in a modport to be a subset (part
> selection)
> of the full port? It is common to see a module using a subset of the bits
> of a signal (both as inputs and outputs.)
>
> I see that one can provide a port expression ( .port_name(expression)
> ), but don't know
> if this is the way to do it.
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
> Co-author "Assertion Based Design"
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625