[sv-bc] SV-BC committee voting results on SV3.1a

Hi All,

Here is SV-BC committee voting results on SV3.1a Draft5 + changes.

SV-BC accepts LRM Draft 5 as the System Verilog 3.1A standard and
recommends forwarding it to the Accellera board for its approval

Agree

Abstain

Oppose

Synopsis

X

Cadence

X

Mentor

X

 Intel

X

 BlueSpec

X

Thank you all for your excellent work and contributions.

--- Johny.

 
Received on Tue Mar 16 08:46:25 2004