Re: [sv-bc] Final voting on sv3.1a Draft 5 + changes

From: Francoise Martinolle <fm@cadence.com>
Date: Mon Mar 15 2004 - 09:51:37 PST

Cadence votes yes on the following statement: "SV-BC accepts LRM Draft 5 as
the System Verilog 3.1A standard and recommends forwarding it to the
Accellera board for its approval."

[ X ] Agree
Received on Mon Mar 15 09:51:43 2004

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