[sv-bc] Final voting on sv3.1a Draft 5 + changes

Hi All,

In continuation to my last note on the voting process (html file is
attached), we have reached the stage of final review of LRM Draft 5 and
proposed changes. Thanks to David Smith, it is all organized under
www.eda.org/sv. It contains draft 5 as well as a list of changes (some
approved and some proposed). We shall review and vote on the proposed
changes on SV-BC sections in our tele-call next Monday, March 15th.

Here is the voting process for SV-BC (which is also similar to SV-EC to
keep consistencies across committees)

1. On the following statement: "SV-BC accepts LRM Draft 5 as the
System Verilog 3.1A standard and recommends forwarding it to the
Accellera board for its approval." Please vote one of the following:

[ ] Agree

[ ] Oppose

[ ] Abstain

2. This is company based voting. Eligible companies (based on
attendance and other Accellera rules) are:

- Synopsis

- Cadence

- Mentor

- Intel

- BlueSpec

3. I would like for each of the above companies to choose a
representative who will send his vote.
4. Company representative will send his/her vote to the chair (
johny.srouji@intel.com) and the co-chair (Karen.Pieper@synopsys.com).
5. The vote closes on 15th March, 2004. The result will be
published on 17th March, 2004.
6. The result and the voting tally will be made public after the
voting period is over.
7. Company representative may make his/her voting preference
public. In that case the vote can be sent to the sv-bc reflector;
however, sv-bc will honor privacy of companies who do not wish to make
their choice public during the voting period.

Thanks,

--- Johny Srouji & Karen Pieper.