RE: [sv-bc] A question about type casting

For some reason I forgot the number of the section 3.16.
What about the term different sizes in section 3.16 bit stream casting?

Could you do the following
typedef reg signed [3:0] tx [7:0];
typedef ref[4:0] ty [8:1];
tx x;
ty y;
assign y = ty'(x);

Dan Jacobi, LVT
Tel : +(972)-4-8655855
INet : 465-5855

-----Original Message-----
From: Paul Graham [mailto:pgraham@cadence.com]
Sent: Wednesday, March 17, 2004 9:50 PM
To: Jacobi, Dan
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] A question about type casting

Dan,

> 1. Does the term different sizes in section refer to the number of
> bits meaning the size of both src_type is 2 bits and the size of
> trg_type is 4 bits, or does the word size refer the number of unpacked
> element / words meaning the size of both src_type and trg_type is 2
> elements. (Do we need any clarification)

The intent is that unpacked arrays must have the same dimension
lengths to be assignment compatible. The element sizes don't have to
be the same. In this way, assignment of one unpacked array to another
is equivalent to the set of assignments of corresponding words in the
arrays. For instance:

    wire signed [3:0] x [7:0];
    wire [4:0] y [8:1];

    assign y = x;

has the same meaning as:

    assign y[8] = x[7]; // sign extend x[7] to five bits
    assign y[7] = x[6]; // sign extend x[6] to five bits
    ...
    assign y[1] = x[0]; // sign extend x[0] to five bits

Verilog is permissive about extending or truncating a word in an
assignment, and that permissiveness extends to assignment of array
elements. But it doesn't make sense to truncate or extend unpacked
arrays by removing or adding whole words. Hence in an assignment the
lengths of each unpacked dimension of the source and target arrays
must match.

Paul
Received on Wed Mar 17 12:43:48 2004