Re: [sv-bc] A question about type casting

> Could you do the following
> typedef reg signed [3:0] tx [7:0];
> typedef ref[4:0] ty [8:1];
> tx x;
> ty y;
> assign y = ty'(x);

I don't see why not. I also don't see why you'd need the type cast.
The two types tx and ty have the same lengths in their corresponding
unpacked array dimensions, so they are already compatible. The only
way in which they differ is that their packed dimensions have
different numbers of bits, but this is handled by standard verilog
rules for sign extension.

Paul
Received on Wed Mar 17 12:51:46 2004