RE: [sv-bc] A question about type casting

Paul and all,

        According to the current definition of casting in 3.16, the
assignment in the mail below is *not* legal. This is because the total
number of bits in tx and ty is different, while explicit casting
currently requires it to be equal.

        It seems very natural for me that wherever an implicit cast
exists, an explicit cast also may be used and would have the same
effect. In the current definition of the language this is not the case,
however, because the following is legal:

typedef reg [3:0] tx [7:0];
typedef reg [4:0] ty [7:0];
tx x;
ty y;
assign y = x;

but the following is *not*:

typedef reg [3:0] tx [7:0];
typedef reg [4:0] ty [7:0];
tx x;
ty y;
assign y = ty'(x); // total number of bits in x is smaller than in y

The question being asked is in fact: is this intentional or a mistake?

Thanks,
____________________

Jacob M. Katz

E-mail: jacob.katz@intel.com
Phone: +972 - 4 - 865 - 5726
iNet: (8) - 465 - 5726

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Paul
Graham
Sent: Wednesday, March 17, 2004 22:52
To: Jacobi, Dan
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] A question about type casting

> Could you do the following
> typedef reg signed [3:0] tx [7:0];
> typedef ref[4:0] ty [8:1];
> tx x;
> ty y;
> assign y = ty'(x);

I don't see why not. I also don't see why you'd need the type cast.
The two types tx and ty have the same lengths in their corresponding
unpacked array dimensions, so they are already compatible. The only
way in which they differ is that their packed dimensions have
different numbers of bits, but this is handled by standard verilog
rules for sign extension.

Paul
Received on Thu Mar 18 10:11:38 2004